Abstract: Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in dynamic logic such as domino is often used in performance critical paths, to achieve high speeds where static CMOS fails to meet performance objectives. However, domino gates typically consume higher dynamic switching and leakage power and display weaker noise immunity as compared to static CMOS gates. Keeping in view of the above stated problems in previous existing designs, novel energy-efficient domino circuit techniques are proposed. The proposed circuit techniques reduced the dynamic switching power consumption; short-circuit current overhead, idle mode leakage power consumption and enhanced evaluation speed and noise immunity in domino logic circuits. Also regarding performance, these techniques minimize the power-delay product (PDP) as compared to the standard full-swing circuits in deep sub micron CMOS technology. Also the noise immunity of the CMOS Domino circuits with various techniques and keepers are analyzed. Various noise sources are considered and noise immune domino logic is proposed.

Salendra Govindarajulu, Dr.T.Jayachandra Prasad, C.Sreelakshmi, Chandrakala and U.Thirumalesh, “Energy-Efficient, Noise-Tolerant CMOS Domino VLSI Circuits in VDSM Technology ” International Journal of Advanced Computer Science and Applications(IJACSA), 2(4), 2011. http://dx.doi.org/10.14569/IJACSA.2011.020417

@article{Govindarajulu2011,
title = {Energy-Efficient, Noise-Tolerant CMOS Domino VLSI Circuits in VDSM Technology },
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2011.020417},
url = {http://dx.doi.org/10.14569/IJACSA.2011.020417},
year = {2011},
publisher = {The Science and Information Organization},
volume = {2},
number = {4},
author = {Salendra Govindarajulu and Dr.T.Jayachandra Prasad and C.Sreelakshmi and Chandrakala and U.Thirumalesh}
}