Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications
DOI: 10.14569/IJACSA.2011.020507
Abstract
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How to Cite this Article
Shukla, N. k., R.K.Singh, & Pattanaik, M. (2011). Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications. International Journal of Advanced Computer Science and Applications, 2(5). https://doi.org/10.14569/IJACSA.2011.020507
Shukla, Neeraj kr, et al.. "Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications." International Journal of Advanced Computer Science and Applications, vol. 2, no. 5, 2011, https://doi.org/10.14569/IJACSA.2011.020507.
@article{Shukla2011,
title = {Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications},
journal = {International Journal of Advanced Computer Science and Applications},
volume = {2},
number = {5},
year = {2011},
publisher = {The Science and Information Organization},
author = {Neeraj kr Shukla and R.K.Singh and Manisha Pattanaik},
doi = {10.14569/IJACSA.2011.020507},
url = {https://doi.org/10.14569/IJACSA.2011.020507}
}
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