Abstract: Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

Ridha SALEM, Yahia SALAH, Imed BENNOUR and Mohamed ATRI, “FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC” International Journal of Advanced Computer Science and Applications(IJACSA), 8(11), 2017. http://dx.doi.org/10.14569/IJACSA.2017.081139

@article{SALEM2017,
title = {FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2017.081139},
url = {http://dx.doi.org/10.14569/IJACSA.2017.081139},
year = {2017},
publisher = {The Science and Information Organization},
volume = {8},
number = {11},
author = {Ridha SALEM and Yahia SALAH and Imed BENNOUR and Mohamed ATRI}
}