Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA
DOI: https://doi.org/10.14569/IJACSA.2017.080621
Abstract
Keywords
How to Cite this Article
Saidani, T. S., & Zayani, H. M. (2017). Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA. International Journal of Advanced Computer Science and Applications, 8(6). https://doi.org/10.14569/IJACSA.2017.080621
Saidani, Taoufik Salem, and Hafedh Mahmoud Zayani. "Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA." International Journal of Advanced Computer Science and Applications, vol. 8, no. 6, 2017, https://doi.org/10.14569/IJACSA.2017.080621.
@article{Saidani2017,
title = {Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA},
journal = {International Journal of Advanced Computer Science and Applications},
volume = {8},
number = {6},
year = {2017},
publisher = {The Science and Information Organization},
author = {Taoufik Salem Saidani and Hafedh Mahmoud Zayani},
doi = {10.14569/IJACSA.2017.080621},
url = {https://doi.org/10.14569/IJACSA.2017.080621}
}
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