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Article Details

Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.

Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA

Author 1: Taoufik Salem Saidani
Author 2: Hafedh Mahmoud Zayani

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Digital Object Identifier (DOI) : 10.14569/IJACSA.2017.080621

Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 8 Issue 6, 2017.

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Abstract: Digital imaging is omnipresent today. In many areas, digitized images replace their analog ancestors such as photographs or X-rays. The world of multimedia makes extensive use of image transfer and storage. The volume of these files is very high and the need to develop compression algorithms to reduce the size of these files has been felt. The JPEG committee has developed a new standard in image compression that now also has the status of Standard International: JPEG 2000. The main advantage of this new standard is its adaptability. Whatever the target application, whatever resources or available bandwidth, JPEG 2000 will adapt optimally. However, this flexibility has a price: the JPEG2000 perplexity is far superior to that of JPEG. This increased complexity can cause problems in applications with real-time constraints. In such cases, the use of a hardware implementation is necessary. In this context, the objective of this paper is the realization of a JPEG2000 encoder architecture satisfying real-time constraints. The proposed architecture will be implemented using programmable chips (FPGA) to ensure its effectiveness in real time. Optimization of renormalization module and byte-out module are described in this paper. Besides, the reduction in computational steps effectively minimizes the time delay and hence the high operating frequency. The design was implemented targeting a Xilinx Virtex 6 and an Altera Stratix FPGAs. Experimental results show that the proposed hardware architecture achieves real-time compression on video sequences on 35 fps at HDTV resolution.

Keywords: MQ-Coder; High speed architecture; FPGA; JPEG2000; VHDL

Taoufik Salem Saidani and Hafedh Mahmoud Zayani, “Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA” International Journal of Advanced Computer Science and Applications(IJACSA), 8(6), 2017. http://dx.doi.org/10.14569/IJACSA.2017.080621

@article{Saidani2017,
title = {Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2017.080621},
url = {http://dx.doi.org/10.14569/IJACSA.2017.080621},
year = {2017},
publisher = {The Science and Information Organization},
volume = {8},
number = {6},
author = {Taoufik Salem Saidani and Hafedh Mahmoud Zayani}
}


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